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Research Papers

Scalable Forming and Flash Light Sintering of Polymer-Supported Interconnects for Surface-Conformal Electronics

[+] Author and Article Information
Harish Devaraj

Department of Mechanical and Aerospace Engineering,
Rutgers University,
98 Brett Road,
Piscataway, NJ 08854
e-mail: harish.devaraj@rutgers.edu

Rajiv Malhotra

Department of Mechanical and Aerospace Engineering,
Rutgers University,
98 Brett Road,
Piscataway, NJ 08854
e-mail: rajiv.malhotra@rutgers.edu

1Corresponding author.

Manuscript received October 8, 2018; final manuscript received January 8, 2019; published online February 28, 2019. Assoc. Editor: Y. Lawrence Yao.

J. Manuf. Sci. Eng 141(4), 041014 (Feb 28, 2019) (10 pages) Paper No: MANU-18-1713; doi: 10.1115/1.4042610 History: Received October 08, 2018; Accepted January 08, 2019

Conformally integrating conductive circuits with rigid 3D surfaces is a key need for smart materials and structures. This paper investigates sequential thermoforming and flash light sintering (FLS) of conductive silver (Ag) nanowire (NW) interconnects printed on planar polymer sheets. The resulting interconnect–polymer assemblies are thus preshaped to the desired 3D geometry and can be robustly attached to the surface. This conformal circuit integration approach avoids interconnect delamination in manual conformation of planar flexible electronics, eliminates heating of the 3D object in direct conformal printing, and enables easy circuit replacement. The interconnect resistance increases after thermoforming, but critically, is reduced significantly by subsequent FLS. The resistance depends nonlinearly on the forming strain, interconnect thickness, and FLS fluence. The underlying physics behind these observations are uncovered by understanding interconnect morphology and temperature evolution during the process. With the optimal parameters found here, this process achieves interconnect resistance of <10 Ω/cm within 90.8 s at 100% maximum strain over a 1 square inch forming area. The application of this process for complex surfaces is demonstrated via a simple conformal LED-lighting circuit. The potential of this approach to enable surface size and material insensitivity, robust integration, and easy replaceability for conformal circuit fabrication is discussed.

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Figures

Grahic Jump Location
Fig. 4

Thermal model with formed PC geometry for ɛm = 100% and the interconnect layer

Grahic Jump Location
Fig. 3

(a) Mold (θm = 100%) used to characterize the effect of thermoforming, (b) mold terminology, and (c) schematic of spatially varying irradiance during FLS of the interconnect–polymer assembly

Grahic Jump Location
Fig. 2

(a) Silver nanowire ink used in this work; schematics of (b) AJP, (c) thermoforming, and (d) FLS

Grahic Jump Location
Fig. 1

Potential paradigm for integration of conformal circuits with rigid 3D surfaces

Grahic Jump Location
Fig. 5

(a) Aerosol-jet printed planar Ag NW interconnect, (b) postformed and post-FLS interconnect–polymer assemblies for different θm, (c) change in resistance for ɛm = 100% with number of printing passes and pulse fluence, and (d) change in resistance with maximum strain for 140 printing passes and 3 J/cm2 pulsefluence (optimal parameters)

Grahic Jump Location
Fig. 6

SEM images of interconnects with 140 printing passes after thermoforming: For ɛm = 100% at (a) root section and (b) top section; (c) ɛm = 30% and (d) ɛm = 100% at the root section

Grahic Jump Location
Fig. 7

Post-FLS SEM images for 3 J/cm2 pulse fluence, 140 printing passes and ɛm = 100% at (a) the root section and (b) the top section; zoomed in views at (c) the root section and (d) the top section; The red dotted circles denote inter-NW necks; Postforming SEM images at the root section for ɛm = 100% for (e) 180 and (f) 140 printing passes

Grahic Jump Location
Fig. 8

Thermal model results for ɛm = 100% formed PC geometry at the peak of third pulse: (a) temperature contours, (b) interconnect temperature as a function of height (c) variation in temperature across the interconnect width, (d) Temperature evolution at the top section of the interconnect for multiple consecutive pulses, and (e) UV–Vis absorption spectrum for unsintered Ag NWs on PC with 100 and 140 printing passes

Grahic Jump Location
Fig. 9

Geometry of PC surface and interconnect for (a) stepped pyramid and (b) stepped dome shape; Demonstration of conformal interconnects using an LED (c) stepped pyramid and (d) Stepped dome shape; (e) Integrated PC–interconnect assemblies

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