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research-article

Micro-structural characterization of thermal damage on silicon wafers sliced using wire-EDM

[+] Author and Article Information
Kamlesh Joshi

Department of Mechanical Engineering, Indian Institute of Technology Bombay, Mumbai, 400076, India
joshi.kamleshmt@gmail.com

Upendra Bhandarkar

Department of Mechanical Engineering, Indian Institute of Technology Bombay, Mumbai, 400076, India
bhandarkar@iitb.ac.in

Indradev Samajdar

Department of Metallurgical Engineering and Materials Science, Indian Institute of Technology Bombay, Mumbai, 400076, India
indra@iitb.ac.in

Suhas S. Joshi

Department of Mechanical Engineering, Indian Institute of Technology Bombay, Mumbai, 400076, India
ssjoshi@iitb.ac.in

1Corresponding author.

ASME doi:10.1115/1.4039647 History: Received December 02, 2017; Revised March 07, 2018

Abstract

Slicing of Si wafers through abrasive processes generates various surface defects on wafers such as cracks and surface contaminations. Also, the processes cause a significant material-loss during slicing and subsequent polishing. Recently, efforts are being made to slice very thin wafers, and at the same time understand the thermal and micro-structural damage caused due to sparking during wire-EDM. Wire-EDM has shown potential for slicing ultra-thin Si wafers of thickness < 200 µm. This work therefore, presents an extensive experimental work on characterization of the thermal damage due to sparking during wire-EDM on ultra-thin wafers. The experiments were performed using RSM-based Central Composite Design (CCD). The damage was mainly characterized by SEM, TEM and Raman spectroscopy. The average thickness of thermal damage on the wafers was observed to be ~16 µm. The damage was highly influenced by exposure time of wafer surface with EDM plasma spark. Also, with an increase in diameter of plasma spark, the surface roughness was found to increase. TEM micrographs have confirmed the formation of amorphous Si along with a region of fine grained Si entrapped inside the amorphous matrix. However, there were no signs of other defects like micro-cracks, twin boundaries or fracture on the surfaces. Micro-Raman spectroscopy revealed that in order to slice a wafer with minimum residual stresses and very low presence of amorphous phases, it should be sliced at the lowest value of pulse on-time and at the highest value of open voltage.

Copyright (c) 2018 by ASME
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