Research Papers

Error Minimization in Layered Manufacturing Parts by Stereolithography File Modification Using a Vertex Translation Algorithm

[+] Author and Article Information
Gaurav Navangul

e-mail: navanggd@mail.uc.edu

Ratnadeep Paul

e-mail: paulrp@ucmail.uc.edu

Sam Anand

e-mail: sam.anand@uc.edu
Center for Global Design and Manufacturing,
School of Dynamic Systems,
Mechanical Engineering Program,
University of Cincinnati,
Cincinnati, OH 45221

1Corresponding author.

Contributed by the Manufacturing Engineering Division of ASME for publication in the Journal of Manufacturing Science and Engineering. Manuscript received January 25, 2012; final manuscript received February 28, 2013; published online May 24, 2013. Assoc. Editor: Robert Landers.

J. Manuf. Sci. Eng 135(3), 031006 (May 24, 2013) (13 pages) Paper No: MANU-12-1026; doi: 10.1115/1.4024035 History: Received January 25, 2012; Revised February 28, 2013

Layered manufacturing (LM) machines use stereolithography (STL) files to build parts by creating continuous slices on top of each other. An STL file approximates the surface of a part with planar triangles. This results in geometric errors being introduced in the part surface during the conversion from the CAD model to the STL file format, which in turn leads to errors in the LM manufactured part. CAD packages have built-in export options to reduce this CAD to STL conversion error. However, this is applied to the entire part geometry which leads to an increase in the file size and preprocessing time in LM machines. This paper presents a new approach to locally reduce this CAD to STL translation error. This approach, referred to as vertex translation algorithm (VTA), compares an STL facet to its corresponding CAD surface, computes the chordal error at multiple points on the STL surface, and translates the point with the maximum chordal error until it lies on the design surface. This translation results in the reduction of the chordal error locally without unnecessarily increasing the size of the STL file. In addition, a facet isolation algorithm (FIA) has also been developed and presented in this paper. This isolation algorithm extracts the STL facets corresponding to the surfaces and features of the part that have to be modified by the translation algorithm. The VTA is applied in conjunction with the FIA on a sample service part to reduce the form and profile error of critical features of the part in order to satisfy the tolerance callouts on the part.

Copyright © 2013 by ASME
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Fig. 3

STL vertices and CAD surface

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Fig. 10

(a) Test surface 1 in NX, (b) test surface 1 in IGES, and (c) STL file for test surface 1

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Fig. 11

(a) Test surface 2 in NX, (b) test surface 2 in IGES, and (c) STL file for test surface 2

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Fig. 12

First VTA iteration for test surface 1

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Fig. 13

Multiple VTA iterations for test surface 1

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Fig. 6

Point of intersection outside the STL facet

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Fig. 7

Vertex translation to create new facets

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Fig. 8

Reduction of chordal error due to VTA

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Fig. 9

Point with maximum chordal error lying on the edge of the STL triangle

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Fig. 1

Chordal error in an STL file

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Fig. 5

Chordal errors at different points in an STL facet

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Fig. 16

(a) Average error versus iteration, and (b) % error reduction versus iteration for test surface 2

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Fig. 18

FIA example, test part 1

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Fig. 19

(a) Extracted NURBS surface from IGES file, and (b) superimposition of bounding box on STL file

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Fig. 20

(a) Intermediate STL file with additional facets, and (b) final STL file with extra facets removed

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Fig. 14

(a) Average error versus iteration, and (b) % error reduction versus iteration for test surface 1

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Fig. 15

Multiple iterations for VTA for test surface 2

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Fig. 24

Comparison of global refinement and VTA approach

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Fig. 25

Test part 1 for applying VTA to minimize cylindricity and surface profile error

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Fig. 26

Test part 1 tolerance specifications

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Fig. 27

Isolated STL feature files using FIA

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Fig. 22

Global refinement of test part 2

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Fig. 23

Selective refinement scheme for test part 2 STL file by VTA

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Fig. 28

Final modified STL file




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