0
RESEARCH PAPERS

Parallelism Improvement of Ground Silicon Wafers

[+] Author and Article Information
S. Matsui, T. Horiuchi

J. Eng. Ind 113(1), 25-28 (Feb 01, 1991) (4 pages) doi:10.1115/1.2899618 History: Received March 01, 1988; Online April 08, 2008

Abstract

This paper discusses substituting grinding for lapping in machining processes of silicon wafers. To attain this goal, the rotating wafer grinding method, in which a rotating wafer is ground by continuous infeed of a cup wheel, is investigated. The parallelism of a silicon wafer ground by this method is within 2 μm for a 5 in. (125 mm) wafer.

Copyright © 1991 by The American Society of Mechanical Engineers
Your Session has timed out. Please sign back in to continue.

References

Figures

Tables

Errata

Discussions

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In